Module 6
Logical Sytnesis
Topics Covered
- Introduction to Synthesis Flow
- RTL to Gate Conversion
- Technology Mapping
- Standard Cell Libraries
- Constraints (SDC)
- Timing Optimization
- Area Optimization
- Power Optimization
- Synthesis Reports Analysis
- Pre-Layout Timing Concepts
- Design Compiler and genus Step by step exicution sample scripts
Module 6 – Study Material (Read Only)
Module 6 – Study Material (Read Only)
Module 6 – Study Material (Read Only)