Module 5
RTL Coding using Verilog
Topics Covered
- Introduction to RTL Design
- Verilog Syntax & Structure
- Data Types & Operators
- Procedural Blocks
- Blocking vs Non-Blocking Assignments
- Combinational Logic Coding
- Sequential Logic Coding
- FSM Design in Verilog
- Testbench Writing
- Simulation Basics
- Coding Guidelines for Synthesis
Module 5 – Study Material (Read Only)