Module 8

Topics Covered

• Introduction to Physical Synthesis
• Difference Between Logical vs Physical Synthesis
• Wire Load Models & Limitations
• Congestion Awareness in Synthesis
• Timing-Driven Optimization Techniques
• Buffer Insertion Concepts
• Gate Sizing & Resizing
• Logic Restructuring Methods
• Physical Constraints Handling
• Impact of Placement Estimation
• Transition & Fanout Optimization
• Physical Synthesis Reports Analysis
• Handoff to Place & Route (PnR)

Module 8 – Study Material (Read Only)