MOSFET

Enhancement NMOSFET (EN-N-MOSFET): Construction and Operation

Introduction

The Enhancement NMOSFET (EN-MOSFET) is one of the most important semiconductor devices used in modern electronic circuits. It belongs to the family of Metal Oxide Semiconductor Field Effect Transistors, where the flow of current between the source and drain is controlled by the electric field produced by the gate voltage. The EN-MOSFET is called an enhancement type device because it is normally OFF and conduction takes place only when the gate voltage exceeds a certain minimum value known as the threshold voltage.

Because of its high input impedance, low power consumption, and excellent switching characteristics, EN-MOSFETs are extensively used in CMOS technology, digital logic circuits, microprocessors, and VLSI systems.

Construction of Enhancement NMOSFET

An Enhancement NMOSFET is fabricated on a p-type semiconductor substrate. Two heavily doped n⁺ regions are diffused into the substrate, which act as the source and drain terminals. The region between these two n⁺ diffusions is where the channel will be formed during operation.

A thin insulating layer of silicon dioxide (SiO₂) is grown over the substrate surface. On top of this oxide layer, a metal gate is deposited. The silicon dioxide layer plays a crucial role by electrically isolating the gate from the substrate, which results in very high input impedance.

The MOSFET is a four-terminal device consisting of:

• Source (S)
  
• Drain (D)
  
• Gate (G)
  
• Body or substrate (B)
  

In most practical circuits, the body terminal is connected to the source to eliminate body effect and simplify operation.

Basic Working Principle

When a positive voltage is applied to the gate, it produces an electric field across the oxide layer. This electric field repels holes from the surface of the p-type substrate and attracts electrons toward the surface. Initially, no channel exists, but as the gate voltage increases, electrons accumulate near the surface and form a thin conducting layer called the n-channel.

The gate structure behaves like a capacitor, with:

• Gate metal as one plate
  
• Channel electrons as the other plate
  
• Silicon dioxide as the dielectric
  

As the gate voltage increases, the conductivity of the channel increases, reducing channel resistance and allowing more current to flow from source to drain when a drain voltage is applied.

Operation of Enhancement NMOSFET

The operation of EN-MOSFET is explained by dividing it into three regions of operation, based on the values of gate-to-source voltage (VGS) and drain-to-source voltage (VDS).

1.2 Operation of Enhancement NMOSFET (EN-MOSFET)

After understanding the construction and basic working principle of the Enhancement NMOSFET, let us now study its operation in detail.
The operation of EN-MOSFET is explained by dividing it into different regions of operation, depending on the values of gate-to-source voltage (VGS) and drain-to-source voltage (VDS).

1. Cut-Off Region (MOSFET OFF Condition)

Case (i): VGS = 0, VDS = 0

In this condition:

• No voltage is applied to the gate.
  
• No voltage is applied between drain and source.
  

Physical Explanation

• The source-to-bulk and drain-to-bulk junctions behave like reverse-biased PN junctions, connected back-to-back.
  
• These reverse-biased junctions offer a very high resistance, typically of the order of 10¹² Ω.
  
• Since there is no channel formed between source and drain, no current flows.
  

 Therefore:

• Drain current ID = 0
  
• MOSFET behaves like an open switch
  

Case (ii): 0 < VGS < VT, VDS = 0

Now a small positive voltage is applied at the gate, but it is less than the threshold voltage (VT).

Step-by-Step Explanation

1. The positive gate voltage induces positive charge on the gate metal.
   
2. This positive charge creates an electric field across the oxide layer.
   
3. The electric field repels holes (majority carriers) from the surface of the p-type substrate.
   
4. As a result, a depletion region is formed under the gate.
   

• This region contains only immobile ions.
  

1. As VGS increases, the depth of the depletion region increases.
   
2. With further increase in VGS, electrons are pulled from the n⁺ source and drain regions toward the surface.
   
3. Initially, a weak inversion layer is formed.
   
4. With sufficient VGS, this weak inversion turns into strong inversion.
   

Strong Inversion

Strong inversion occurs when:

• The concentration of electrons at the surface becomes equal to the concentration of holes in the p-type substrate.
  

At this point, a conducting n-channel is formed between the source and drain.

Threshold Voltage (VT)

• Threshold voltage (VT) is the minimum gate-to-source voltage (VGS) required to create strong inversion and hence a conducting channel.
  
• The electric field due to VGS acts in the vertical direction, perpendicular to the substrate.
  

Before VT:

• Channel does not exist
  
• ID ≈ 0
  

2. Triode (Linear) Region

Once VGS exceeds VT, the MOSFET enters the conduction mode.

Condition (iii): VGS > VT, VDS > 0 and VDS < (VGS − VT)

Physical Explanation

1. A uniform n-channel is formed between source and drain.
   
2. Applying VDS creates a horizontal electric field from drain to source.
   
3. Due to this field, electrons move from source to drain, producing drain current ID.
   
4. If VGS is increased much more than VT (VGS >> VT):
   

• The channel becomes deeper and more conductive
  
• This additional voltage is called overdrive voltage
   Overdrive Voltage=VGS−VT ext{Overdrive Voltage} = VGS - VTOverdrive Voltage=VGS−VT

1. For a fixed VGS, as VDS increases slightly:
   

• ID increases linearly
  
• The channel behaves like a resistor
  

 Hence, this region is also called the linear region or ohmic region.

Condition (iv): VGS > VT, VDS > 0 but still VDS < (VGS − VT)

As VDS increases further:

1. The gate-to-channel potential is no longer uniform.
   
2. The channel becomes:
   

• Deeper near the source
  
• Shallower near the drain
  

1. This happens because the effective gate voltage near the drain is reduced due to higher drain potential.
   

Still:

• Channel exists throughout
  
• Current continues to increase
  

Pinch-Off Condition

When:

VDS=VGS−VTVDS = VGS - VTVDS=VGS−VT

• The channel gets pinched off at the drain end
  
• This value of VDS is called VDS(sat)
  

3. Saturation Region

Condition (v): VGS > VT and VDS ≥ (VGS − VT)

Detailed Explanation

1. When VDS exceeds VDS(sat):
   

• The channel near the drain end is fully pinched off.
  

1. Due to velocity saturation of carriers and the strong electric field at the drain end:
   

• Electrons are swept quickly from the channel.
  

1. Increasing VDS further:
   

• Enlarges the depletion region at the drain
  
• Eats into the channel from the drain side
  

1. The channel depth near the source remains greater than near the drain.
   

Important Result

• Drain current ID becomes constant
  
• ID is independent of VDS
  
• ID depends only on VGS
  

 This is why this region is called the saturation region.

V-l characteristics of N-MOSFET

Transfer characteristics of N-MOSFET

Summary of N-MOSFET Operation

Enhancement P MOSFET (EN-P-MOSFET):

Construction and Operation (Corrected & Verified)

 Important note before reading
 For PMOSFET, voltages are negative with respect to the source.
To avoid confusion, absolute-value (magnitude) form is used in equations, which is the standard academic practice.

Introduction

The Enhancement PMOSFET (EN-PMOSFET) is a voltage-controlled semiconductor device belonging to the MOSFET family. It is called an enhancement type device because no channel exists at zero gate voltage, and conduction occurs only when the gate voltage is made sufficiently negative relative to the source.

PMOSFETs conduct using holes as majority carriers and are extensively used along with NMOSFETs in CMOS technology, enabling low-power and high-density integrated circuits.

Construction of Enhancement PMOSFET

• Fabricated on an n-type substrate
  
• Two heavily doped p⁺ regions form:
  

• Source
  
• Drain
  

• A thin SiO₂ layer is grown on the substrate
  
• A metal gate is deposited on the oxide
  

The oxide electrically isolates the gate, resulting in very high input impedance.

The PMOSFET has four terminals:

• Source (S)
  
• Drain (D)
  
• Gate (G)
  
• Body (B)
  

 In practice, body is connected to source to avoid body effect.

Basic Working Principle

When the gate is made negative with respect to the source, an electric field is established across the oxide layer.

This electric field:

• Repels electrons from the surface of the n-substrate
  
• Attracts holes toward the surface
  

Initially, no channel exists. As the magnitude of negative gate voltage increases, holes accumulate and form a p-type inversion layer (p-channel) connecting source and drain.

The gate acts like a capacitor:

• Gate metal → one plate
  
• Channel holes → second plate
  
• SiO₂ → dielectric
  

Increasing |VGS| increases channel conductivity.

Operation of Enhancement PMOSFET

The operation is divided into three regions, based on VGS and VDS.

 To keep equations correct and simple, we use magnitude form:

• |VGS| = magnitude of gate-to-source voltage
  
• |VDS| = magnitude of drain-to-source voltage
  
• |VT| = magnitude of threshold voltage
  

1. Cut-Off Region (PMOS OFF)

Condition

Explanation

• Gate voltage is not sufficiently negative
  
• No inversion layer is formed
  
• Source-to-bulk and drain-to-bulk junctions are reverse biased
  
• Effective resistance ≈ 10¹² Ω
  

 Drain current:

ID=0I_D = 0ID​=0

PMOS behaves like an open switch.

2. Triode (Linear / Ohmic) Region

Condition

Explanation

• A continuous p-channel is formed
  
• Applying VDS creates a horizontal electric field
  
• Holes flow from source to drain
  
• Channel exists along the entire length
  

As |VDS| increases (small values):

• Drain current increases linearly
  
• Device behaves like a voltage-controlled resistor
  

Drain Current Equation (Triode Region)

Where:

• μₚ = hole mobility
  
• Cox = oxide capacitance per unit area
  
• W/L = channel width-to-length ratio
  

Overdrive Voltage

This controls channel depth and conductivity.

Pinch-Off Condition

Pinch-off occurs when:

This value of drain voltage is called:

3. Saturation Region

Condition

Explanation

• Channel is pinched off at the drain end
  
• Strong electric field sweeps carriers
  
• Increasing |VDS| further:
  

• Increases depletion width
  
• Does NOT increase drain current
  

Drain current becomes independent of VDS.

Drain Current Equation (Saturation Region)

Key Result

• ID depends only on VGS
  
• PMOS behaves like a constant current source
  

V–I Characteristics of PMOSFET

• Shows ID vs VDS
  
• Clearly indicates:
  

• Cut-off
  
• Triode
  
• Saturation regions
  

Transfer Characteristics of PMOSFET

• Shows ID vs VGS
  
• Used to determine:
  

• Threshold voltage
  
• Transconductance

Depletion MOSFET :

The construction of depletion MOSFET is the same as enhancement MOSFET but the conduction channel that is formed is already implanted but not induced. The below table gives the information on the DE-MOSFET.

3. Introduction to CMOS Technology

The term CMOS stands for Complementary Metal Oxide Semiconductor. CMOS technology is one of the most widely used technologies in modern electronic system design, especially in the computer chip and integrated circuit industry. Today, CMOS forms the backbone of almost all digital integrated circuits, ranging from simple logic gates to complex microprocessors and memory devices.

The word “complementary” in CMOS refers to the use of two complementary types of MOSFETs, namely:

• NMOS (n-channel MOSFET) and
  
• PMOS (p-channel MOSFET)
  

These two transistors are connected in such a way that when one transistor is ON, the other is OFF. This complementary operation is the key reason for the very low power consumption of CMOS circuits.

Basic Concept of CMOS Operation

In CMOS technology, NMOS and PMOS transistors are paired together to perform logic operations. The most basic and important CMOS circuit is the CMOS inverter.

• The PMOS transistor is connected between the output and the power supply (VDD).
  
• The NMOS transistor is connected between the output and ground (GND).
  
• Both gates are connected together and act as the input.
  
• The drains of both transistors are connected together and form the output.
  

Because of this arrangement:

• When the input is LOW, PMOS turns ON and NMOS turns OFF → output becomes HIGH.
  
• When the input is HIGH, NMOS turns ON and PMOS turns OFF → output becomes LOW.
  

Thus, CMOS provides a full logic swing, meaning the output voltage levels are very close to the supply voltages.

CMOS Inverter – Importance

The CMOS inverter is considered the building block of all CMOS logic circuits. Using CMOS inverters, we can construct:

• NAND gates
  
• NOR gates
  
• Flip-flops
  
• Adders
  
• Multiplexers
  
• Memory cells
  

Hence, understanding CMOS inverter operation is essential for learning digital electronics, VLSI design, and CMOS circuit design.

Why CMOS Technology Is Widely Used

CMOS technology has become dominant in the semiconductor industry due to several important advantages.

Advantages of CMOS Technology

1. Very Low Power Consumption

In steady state, CMOS circuits draw almost zero static power, because there is no direct path between VDD and GND. Power is consumed mainly during switching.

2. High Noise Immunity

CMOS circuits have large noise margins, making them highly resistant to electrical noise and voltage fluctuations.

3. High Input Impedance

The gate of a MOSFET is insulated by silicon dioxide, resulting in very high input impedance. This reduces loading effects on previous stages.

4. Full Voltage Swing

CMOS outputs switch between nearly 0 V and VDD, ensuring reliable logic levels.

5. High Packing Density

CMOS technology allows very large numbers of transistors to be fabricated on a single chip, which is essential for VLSI and ULSI designs.

6. Scalability

CMOS technology scales well with device size reduction, enabling smaller, faster, and more efficient chips.

Limitations of CMOS Technology

Although CMOS technology has many advantages, it also has some limitations that must be understood.

1. Dynamic Power Dissipation

Power is consumed during switching due to:

• Charging and discharging of load capacitances
  
• Short-circuit current during transition
  

As operating frequency increases, dynamic power consumption increases.

2. Sensitive to Static Discharge

MOSFET gates are sensitive to electrostatic discharge (ESD) because of the thin oxide layer, which can get damaged easily.

3. Fabrication Complexity

CMOS fabrication is more complex than single-transistor technologies because it requires:

• Both NMOS and PMOS fabrication
  
• Additional processing steps
  

4. Latch-Up Problem

CMOS circuits may suffer from latch-up, a condition where a low-resistance path forms between VDD and GND, causing excessive current flow if not properly designed.

3.1 Structure and Working of CMOS Logic

In CMOS (Complementary Metal Oxide Semiconductor) technology, both N-type MOSFETs (NMOS) and P-type MOSFETs (PMOS) are used together to implement logic functions. The fundamental idea of CMOS operation is complementary action, meaning that:

The same input signal that turns ON one type of transistor turns OFF the other type.

This complementary behavior ensures that only one conduction path exists at a time, either to the power supply or to ground, but never both simultaneously in steady state. Because of this property, CMOS circuits do not require pull-up resistors, unlike NMOS-only logic families.

Pull-Up and Pull-Down Networks

In CMOS logic gates, transistors are organized into two distinct networks:

1. Pull-Down Network (PDN)

• Constructed using NMOS transistors
  
• Connected between the output node and the low-voltage rail (VSS or ground)
  
• When the PDN is ON, it pulls the output to logic ‘0’

2. Pull-Up Network (PUN)

• Constructed using PMOS transistors
  
• Connected between the output node and the high-voltage rail (VDD)
  
• When the PUN is ON, it pulls the output to logic ‘1’

These two networks are designed such that:

• When PDN conducts, PUN is OFF
  
• When PUN conducts, PDN is OFF
  

This arrangement guarantees low static power consumption and reliable logic levels.

Basic Working Principle

• Input voltage is applied simultaneously to the gates of NMOS and PMOS
  
• Depending on the input level:
  

• Either the pull-up path or the pull-down path becomes active
  

• The output node is connected either to VDD or to GND, but never both
  

This switch-like behavior allows CMOS circuits to be modeled as ideal logic switches, improving efficiency and noise immunity.

3.2 CMOS Characteristics / Advantages (with Pull-Up and Pull-Down Operation)

CMOS technology is widely used because it offers:

• High operating speed
  
• Very low power dissipation
  
• Large noise margins
  
• Operation over a wide range of supply voltages
  

To understand these advantages clearly, let us analyze the pull-up and pull-down transistor behavior using a load capacitor (C₁), which represents the output capacitance.

Operation of Pull-Down Transistor (NMOS)

Condition: VGS > VTN (NMOS ON)

• At Vcs > VTNMOS is ON
• The capacitor (C1) charges tillVDD-Vtn
• The C1 charges > VDD-Vtn NMOS become OFF as VGs <Vtn
• So NMOS act as a weak 1

• At VGs< VtpPMOS is ON VDD
• The capacitor (C1) charge up to VDD
• Therefore, PMOS acts as a strong 'L'
• The capacitor (C1) charge up to Pull-up and Pull-down transistors

  ---

Pull down makes a connection from output t ground Channel gets formed between drawn and source. NMOS is ON at VGs>V: The C1 gets discharged to OV after this channel is formed

• At Vcs< Vt→ PMOS ON
• Channel gets formed between drawn and source
•  C1 gets discharged to Vip after the channel has formed
• PMOS acts as weak 0.

Charging and Discharging of Output Capacitor (C₁)

Charging Phase

• PMOS ON, NMOS OFF
  
• C₁ charges through PMOS
  
• Output rises toward VDD
  

Discharging Phase

• NMOS ON, PMOS OFF
  
• C₁ discharges through NMOS
  
• Output falls toward 0 V
  

This charging and discharging mechanism determines:

• Propagation delay
  
• Dynamic power dissipation
  
• Switching speed
  

Why CMOS Has Low Power Dissipation

• In steady state:
  

• Either PMOS or NMOS is OFF
  
• No direct path between VDD and GND
  

• Power is consumed mainly:
  

• During switching
  
• Due to capacitor charging/discharging
  

This makes CMOS ideal for battery-powered and low-power applications.

3.3 Noise Margin in CMOS Circuits

Introduction

In practical digital circuits, signals are never perfectly clean. During transmission, digital signals are often affected by noise due to coupling, interference, switching transients, or external disturbances. Noise margin is a critical parameter that determines how much noise a CMOS circuit can tolerate without affecting correct logic operation.

In simple terms, noise margin is the maximum noise voltage that a circuit can withstand while still interpreting the signal correctly. A larger noise margin means better reliability and robustness of the digital system.

Digital Signal Levels and Noise
Digital logic levels are not represented by single fixed voltages, but rather by ranges of voltages. This is what allows CMOS circuits to operate correctly even when noise is present.

To understand noise margin, we must first define the critical voltage levels that characterize the DC input–output behavior of a CMOS inverter.

Critical Voltage Levels in a CMOS Inverter

A CMOS inverter is characterized by five important voltage parameters:

1. VOH (Maximum Output High Voltage)

• The minimum voltage at the output that is guaranteed to represent logic ‘1’
  
• Ideally close to VDD
  

2. VOL (Maximum Output Low Voltage)

• The maximum voltage at the output that is guaranteed to represent logic ‘0’
  
• Ideally close to 0 V
  

3. VIH (Minimum Input High Voltage)

• The minimum input voltage that the inverter will interpret as logic ‘1’
  

4. VIL (Maximum Input Low Voltage)

• The maximum input voltage that the inverter will interpret as logic ‘0’
  

5. Vth (Switching Threshold Voltage)

• The input voltage at which the inverter switches from logic ‘1’ to logic ‘0’
  
• Typically near VDD / 2 for symmetric CMOS inverters
  

Interpretation of Input and Output Voltage Ranges

Based on these voltage levels:

Input Logic Levels

• Any input voltage between 0 and VIL is interpreted as logic ‘0’
  
• Any input voltage between VIH and VDD is interpreted as logic ‘1’
  
• Input voltages between VIL and VIH fall in the undefined region and may cause incorrect operation
  

Output Logic Levels

• Any output voltage between 0 and VOL is interpreted as logic ‘0’
  
• Any output voltage between VOH and VDD is interpreted as logic ‘1’
  

This separation into voltage ranges allows CMOS circuits to tolerate noise.

Noise Tolerance Using Cascaded Inverters

Consider a chain of three cascaded CMOS inverters.

Low-Level Noise Case

• Assume the output of the first inverter is VOL, representing logic ‘0’
  
• During signal transmission, noise may increase the voltage slightly
  
• If the input voltage of the second inverter remains below VIL, it is still correctly interpreted as logic ‘0’
  
• If noise raises the voltage above VIL, the inverter may misinterpret the signal
  

 Therefore, VIL is the maximum allowable noisy voltage that can still be recognized as logic ‘0’.

High-Level Noise Case

• Assume the output of the second inverter is VOH, representing logic ‘1’
  
• Noise may reduce the voltage during transmission
  
• If the input voltage of the third inverter remains above VIH, it is correctly interpreted as logic ‘1’
  
• If the voltage drops below VIH, incorrect interpretation may occur
  

 Therefore, VIH is the minimum allowable noisy voltage that can still be recognized as logic ‘1’.

Definition of Noise Margins

Based on the above discussion, noise margins are defined as the difference between output voltage levels and corresponding input voltage limits.

Noise Margin Low (NML)

​

• Represents the maximum noise voltage that can be added to a logic ‘0’ signal without causing an error
  

Noise Margin High (NMH)

• 
• Represents the maximum noise voltage that can be subtracted from a logic ‘1’ signal without causing an error
  

Importance of Noise Margin in CMOS

• Larger noise margins improve noise immunity
  
• Ensure reliable signal transmission across multiple logic stages
  
• Allow CMOS circuits to operate correctly in noisy environments
  
• One of the major reasons CMOS technology dominates VLSI and digital IC design
  

Conclusion

Noise margin is a key measure of the robustness of CMOS digital circuits. By defining voltage ranges instead of fixed logic levels, CMOS inverters can tolerate significant noise without malfunction. The high noise margins of CMOS technology ensure stable operation even in the presence of interference, making CMOS ideal for high-speed, low-power, and large-scale integrated systems.

3.4 CMOS Inverter

Introduction

The CMOS inverter is the most fundamental and important building block in CMOS digital design. Almost all complex CMOS logic circuits such as NAND gates, NOR gates, flip-flops, adders, and memory cells are ultimately built using CMOS inverters. Understanding its structure, operation, voltage transfer characteristics, dynamic behavior, and power dissipation is therefore essential.

A CMOS inverter consists of one PMOS transistor and one NMOS transistor connected in a complementary manner. The input signal A is applied simultaneously to the gate terminals of both transistors, while the drains are connected together to form the output.

Structure and Basic Operation of CMOS Inverter

• The PMOS transistor is connected between the output and the positive supply voltage (VDD).
  
• The NMOS transistor is connected between the output and the ground (VSS).
  
• The input A controls both transistors simultaneously.
  

Input Low Condition

When a low voltage is applied at the input terminal A:

• The NMOS transistor turns OFF and behaves like an open circuit
  
• The PMOS transistor turns ON
  
• The output node is connected to VDD
  
• Output voltage becomes logic ‘1’ (VOH)
  

Thus, the output is pulled upwards.

Input High Condition

When a high voltage is applied at the input terminal A:

• The PMOS transistor turns OFF and behaves like an open circuit
  
• The NMOS transistor turns ON
  
• The output node is connected to VSS (ground)
  
• Output voltage becomes logic ‘0’ (VOL)
  

Thus, the output is pulled downwards.

This complementary switching action ensures low static power dissipation and full voltage swing.

Voltage Transfer Characteristics (VTC) of CMOS Inverter

The Voltage Transfer Characteristic (VTC) represents the relationship between:

• Vin (input voltage)
  
• Vout (output voltage)
  

The VTC curve is obtained by plotting Vout versus Vin and provides critical insight into:

• Noise margins
  
• Switching threshold
  
• Stability of logic levels
  
  
  

Load Line Plot Concept

The VTC of a CMOS inverter can be derived graphically using a load-line plot.

Basic Idea

The load-line plot is obtained by superimposing the I–V characteristics of NMOS and PMOS transistors on a common coordinate system.

To achieve this, the following transformations are used:

The PMOS characteristics are obtained by:

• Mirroring around the x-axis
  
• Shifting horizontally by VDD
  

DC Operating Points

For a valid DC operating point:

• The drain current through NMOS must equal the drain current through PMOS
  

Graphically:

• DC operating points are located at the intersection of the NMOS and PMOS load lines
  

It is observed that:

• Most operating points lie near VOH or VOL
  
• The transition region is very narrow
  

This explains the steep slope of the CMOS inverter VTC.

Region-Wise Analysis of VTC

The VTC can be divided into five regions:

Region A

• 
  
• NMOS is cut-off
  
• PMOS is ON (linear region)
  
• Output voltage:
  

Region B

• 
• NMOS is ON (saturation)
  
• PMOS is ON (linear)
  
• At:
  
• Output remains close to VOH
  

Region C (Switching Threshold Region)

• 
  
• Both NMOS and PMOS operate in saturation
  
• This is the inverter threshold voltage
  

Region D

• 
• NMOS is linear
  
• PMOS is saturation
  
• Slope:

• Output voltage approaches VOL
  

Region E

• 
• NMOS is ON (linear)
  
• PMOS is OFF
  
• Output voltage:
  

  ---

MOSFET Capacitances in CMOS Inverter

MOSFETs exhibit several parasitic capacitances that significantly affect dynamic behavior.

Lumped representation of parasitic MOSFET capacitances

Types of Capacitances

1. Overlap (Structure-Induced) Capacitance
   

1. Channel Capacitances
   

1. Diffusion Capacitances
   

CMOS Parasitic Capacitance Model

For simplicity in analysis:

• All parasitic capacitances are lumped into a single load capacitance CLC_LCL​
  
• CLC_LCL​ is assumed to be connected between Vout and ground
  

This simplified model is used to analyze:

• Transient behavior
  
• Propagation delay
  
• Power dissipation
  

Propagation Delay in CMOS Inverter

Propagation delay is the time required for a change at the input to reflect at the output.

Definitions

• TPHL: Delay during high-to-low output transition
  
• TPLH: Delay during low-to-high output transition
  

Measured between 50% voltage points of input and output waveforms.

RC Delay Model

The CMOS inverter behaves like a first-order RC network.

The average propagation delay is:

Dynamic Power Dissipation

Each time the output switches:

• Load capacitor CLC_LCL​ is charged and discharged
  

Energy Considerations

• Energy drawn from supply:
  
• Energy stored in capacitor:
  

Dynamic Power Equation

If switching occurs f0→1f_{0→1}f0→1​ times per second:

Power Dissipation Due to Direct-Path Current

Due to finite input rise and fall times:

• NMOS and PMOS conduct simultaneously for a short duration
  
• This creates a direct path current between VDD and GND
  

Energy consumed per switching:

Static Power Dissipation

Static power dissipation is given by:

Ideally:

• 
• Because NMOS and PMOS are never ON simultaneously in steady state
  

In practice:

• Small leakage currents exist
  
• Usually negligible compared to dynamic power
  

Conclusion

The CMOS inverter exhibits excellent performance due to its complementary structure. Its steep voltage transfer characteristics provide high noise immunity, while its low static power consumption makes it ideal for modern digital systems. The combined understanding of VTC, parasitic capacitances, propagation delay, and power dissipation is crucial for designing efficient CMOS logic circuits.

4. Short Channel Effects

4. Introduction

A MOS transistor is referred to as a short channel device when its physical channel length becomes comparable to the depletion region widths of the source and drain junctions. In modern VLSI technologies, aggressive scaling has reduced the effective channel length (L_{eff}) to values close to the source/drain junction depth (x_j). Under such conditions, the assumptions used for long-channel MOSFET operation no longer remain valid.

Short channel effects (SCEs) arise mainly due to two fundamental physical causes:

1. Limitations on carrier transport caused by very high electric fields in the channel.
2. Electrostatic interactions between the drain, source, and channel, which modify the threshold voltage and degrade gate control.

As device dimensions continue to shrink, understanding and mitigating short channel effects has become a critical aspect of CMOS circuit and process design.

4.1 Channel Length Modulation (CLM)

In an ideal long-channel MOSFET operating in saturation, the drain current is independent of the drain-to-source voltage (V_{DS}). However, in short-channel devices, this assumption no longer holds due to channel length modulation.

Physical Explanation

As (V_{DS}) increases beyond the saturation voltage:

• The pinch-off point near the drain moves slightly toward the source.
• The voltage across the channel remains approximately equal to the overdrive voltage (V_{ov} = V_{GS} - V_T).
• The additional drain voltage drops across the depletion region between the channel end and the drain.

As the drain depletion region widens, it encroaches into the channel region, effectively reducing the channel length from (L) to (L - Delta L). Since the drain current is inversely proportional to the channel length, this reduction causes the drain current to increase with increasing (V_{DS}).

This phenomenon is called channel length modulation and is more pronounced in advanced technologies with very small channel lengths.

Modified Drain Current Equation

The effect of channel length modulation is incorporated into the drain current equation as:

Where:

• (lambda) is the channel length modulation parameter (V⁻¹)
• Its value depends on fabrication technology and channel length

4.2 Drain-Induced Barrier Lowering (DIBL)

Drain-Induced Barrier Lowering is a major short channel effect resulting from excessive electrostatic coupling between the drain and the channel.

Physical Mechanism

In a long-channel MOSFET:

• Increasing drain voltage does not significantly affect the source-channel potential barrier.
• Drain current remains controlled primarily by the gate voltage.

In a short-channel MOSFET:

• Increasing drain bias lowers the conduction band energy at the drain.
• The drain depletion region expands toward the source.
• This reduces the source-to-channel potential barrier, even without increasing the gate voltage.

As a result, carriers can flow from source to drain at lower gate voltages, effectively reducing the threshold voltage.

Consequences of DIBL

• Increased off-state leakage current
• Reduced threshold voltage with increasing (V_{DS})
• Loss of gate control over channel conduction

DIBL may eventually lead to punch-through, where the source and drain depletion regions merge.

Mitigation

• Applying reverse substrate bias to increase source barrier height
• Using shallow source/drain junctions
• Increasing channel doping near the source

4.3 Velocity Saturation

In long-channel MOSFETs, carrier velocity is proportional to the electric field:
[
v_d = mu E
]

However, in short-channel devices, the electric field along the channel becomes extremely high, causing carriers to reach a maximum velocity limit known as velocity saturation.

Impact on Drain Current

• Carrier velocity no longer increases linearly with electric field
• Drain current saturates earlier than predicted by long-channel models
• Saturation occurs before (V_{DS} = V_{GS} - V_T)

Modified Drain Current Behavior

• The saturation current shows a linear dependence on (V_{GS}) instead of a quadratic dependence
• This reduces the current drive capability of short-channel devices

Velocity saturation effects are generally less severe in PMOS devices due to lower hole mobility.

4.4 Subthreshold Conduction (Weak Inversion)

In an ideal switch, drain current should abruptly drop to zero when (V_{GS} < V_T). In reality, MOSFETs conduct a small current even below threshold voltage.

Explanation

• For (V_{GS} < V_T), a weak inversion layer exists
• Carriers move by diffusion rather than drift
• Drain current decreases exponentially with decreasing (V_{GS})

This behavior resembles that of a bipolar transistor and is called subthreshold conduction.

Subthreshold Slope (S)

The quality of turn-off is measured using the subthreshold slope:
[
S = n rac{kT}{q} ln(10)
]

• Ideal value: 60 mV/decade at room temperature
• Practical values are higher due to short channel effects

Lowering supply voltage requires careful control of (V_T) to limit subthreshold leakage.

4.5 Hot Carrier Effects (HCE)

As device dimensions shrink while supply voltages remain high, electric fields near the drain increase significantly.

Physical Mechanism

• High-energy electrons gain sufficient kinetic energy
• Electrons may enter the gate oxide
• Trapped charges modify threshold voltage

Effects include:

• Increase in NMOS threshold voltage
• Decrease in PMOS threshold voltage
• Long-term reliability degradation

Modern processes reduce HCE using lightly doped drain (LDD) structures.

4.6 Gate-Induced Drain Leakage (GIDL)

GIDL is an off-state leakage mechanism observed at high drain voltage and low or negative gate bias.

Explanation

• Strong electric field at gate-drain overlap
• Narrow depletion region in heavily doped drain
• Band-to-band tunneling occurs
• Generated electrons flow to the drain

GIDL is not due to oxide tunneling but occurs entirely within the silicon.

4.7 Body Bias (Body Effect / Short Channel Variant)

In short-channel MOSFETs, the body effect becomes more pronounced due to stronger coupling between the channel and substrate.

Impact

• Threshold voltage varies with substrate bias
• Increased sensitivity of Vt to body potential
• Degraded noise margins and stability

This effect is exploited intentionally in adaptive body-biasing techniques.

4.8 Electromigration

Electromigration is a reliability issue caused by prolonged current flow in metal interconnects.

Key Points

• Metal ions drift under high current density
• Causes opens or shorts over time
• Strongly dependent on temperature and current density

Mitigation techniques include:

• Wider interconnects
• Copper metallization
• Alloying aluminum with Cu

4.9 CMOS Latch-Up

CMOS processes inherently form parasitic bipolar transistors, creating an n-p-n-p thyristor structure.

Latch-Up Mechanism

• Triggered by transient currents or voltage spikes
• Creates low-resistance path between VDD and VSS
• Leads to excessive current and device failure

Prevention Techniques

• Guard rings
• Multiple well and substrate contacts
• Low-resistance wells and substrates

Conclusion

Short channel effects significantly impact the performance, power consumption, and reliability of modern CMOS devices. As technology scales further, careful device engineering, circuit techniques, and layout strategies are required to control these effects and ensure robust operation of VLSI systems.