Module 15

Topics Covered

• CTS role in Timing Closure (why CTS is needed)
• Pre-CTS vs Post-CTS timing differences
• Clock definitions review (create_clock, generated clocks)
• Clock latency types: source latency vs network latency
• Clock skew basics: global skew, local skew, target skew
• Clock uncertainty: jitter, variation, margin concepts
• Clock tree objectives: skew, latency, slew, power, noise
• Clock topology options: H-tree / spine / mesh (conceptual)
• Clock tree elements: buffers, inverters, integrated clock gates (ICG)
• Clock gating awareness: ICG placement considerations, enable timing
• Clock tree constraints: max transition (slew), max capacitance, max fanout
• Clock concurrent optimization idea (clock + timing together)

📚 Part B: CTS Build (Implementation)

• Clock net identification and grouping
• Skew Groups: definition, usage, multi-domain considerations
• Clock balancing concepts (matching path delays)
• Buffer/inverter insertion strategies (depth, branching)
• Clock trunk vs leaf strategy (concept)
• Handling multi-clock & async clocks at CTS stage (high-level)
• CTS quality checks: skew, latency, transition, insertion delay
• CTS reporting and interpretation (clock tree reports)

📚 Part C: Signal Integrity in CTS (Noise / Crosstalk / NDR)

• Xtalk fundamentals: coupling capacitance and aggressor/victim concept
• Xtalk impact on clock: jitter-like behavior, pulse distortion, delay shift
• Xtalk analysis for clocks: when/why to analyze during CTS
• Clock shielding concepts (shield nets, shielding strategy)
• NDR Rules for clock nets: wider wires, higher spacing, preferred layers
• Spacing-based noise reduction vs shielding trade-offs
• Clock net routing layer strategy (upper metal usage concept)
• EM/IR awareness for clock network (why clocks are sensitive)