CORE THEORY

STUDY MATERIALS

Access premium, well-structured notes, flow diagrams, and deep-dive reference materials covering the entire ASIC Physical Design flow.

18 Comprehensive Modules

MODULE 1

Introduction to Electronics

Basic electronics fundamentals and semiconductor physics.

MODULE 2

MOSFET & CMOS Theory

Deep dive into transistor operation and CMOS fabrication.

MODULE 3

Digital Electronics

Logic gates, boolean algebra, and sequential circuits.

MODULE 4

Linux & Basic Tcl Script

Essential OS commands and scripting for VLSI.

MODULE 5

RTL Coding using Verilog

Hardware description language basics and RTL design.

MODULE 6

Logical Synthesis

Converting RTL into technology-mapped gate-level netlists.

MODULE 7

Design For Testability

DFT concepts, scan insertion, and fault models.

MODULE 8

Physical Synthesis

Placement-aware synthesis and optimization techniques.

MODULE 9

Static Timing Analysis - 1

Fundamentals of STA, setup/hold checks, and constraints.

MODULE 10

Static Timing Analysis - 2

Advanced STA concepts, crosstalk, and OCV.

MODULE 11

Static Timing Analysis - 3

Signoff timing closure and ECO generation.

MODULE 12

PNR Inputs & Sanity Checks

Library preparation, netlist sanity, and SDC validation.

MODULE 13

FloorPlan & PowerPlan

Macro placement, IO rings, and robust power grid design.

MODULE 14

Placement

Standard cell placement and congestion mitigation.

MODULE 15

Clock Tree Synthesis - 1

Building zero-skew clock networks and balancing.

MODULE 16

Clock Tree Synthesis - 2

Advanced CTS routing, NDR rules, and power optimization.

MODULE 17

Routing

Global and detail routing, fixing DRCs and antennas.

MODULE 18

Physical Verification & Signoff

Final DRC/LVS/ERC checks and tapeout readiness.