Question 1

What is the primary objective of Floorplanning in VLSI Physical Design?

Accepted Answer

Floorplanning is the initial phase of physical implementation where die size, core boundary, I/O pad placement, macro placement, and power grid network (PGN) architecture are defined. The goal is to minimize total die area, prevent routing congestion, reduce total wire length, and optimize timing paths before standard cell placement. Proper macro placement with adequate halo spacing prevents macro blockage and thermal hotspots.

Question 2

What is the difference between Global Placement and Detailed Placement?

Accepted Answer

Global Placement positions standard cells across the die area to minimize overall wirelength and path delays without strictly enforcing non-overlapping cell grid boundaries. Detailed Placement follows Global Placement and legalizes cell positions by placing them strictly into standard cell rows, eliminating cell overlaps while minimizing total displacement and wirelength penalty.

Question 3

Why is Clock Tree Synthesis (CTS) necessary, and what is the difference between clock latency and clock skew?

Accepted Answer

CTS builds a balanced buffer tree network from the clock source (PLL) to all sequential flip-flop clock pins to ensure synchronous timing across the chip. Clock Latency is the total insertion delay from clock source to a specific flip-flop pin. Clock Skew is the maximum difference in clock arrival times between two communicating flip-flops. Minimizing clock skew prevents setup and hold timing violations.

Question 4

How do you resolve a Setup timing violation versus a Hold timing violation?

Accepted Answer

Setup timing violations occur when data arrives too late at the capture flip-flop before the active clock edge. Setup issues are fixed by swapping to high-speed low-VT (LVT) cells, upsizing buffers, reducing routing wirelength, or restructuring logic. Hold timing violations occur when data changes too quickly before the hold window closes. Hold violations are independent of clock period and are fixed by inserting delay buffers or delay cells along the data path.

Question 5

What are the key stages of Routing in ASIC physical design?

Accepted Answer

Routing connects standard cell pins and macro terminals using metal layers according to the netlist. It consists of Global Routing (which assigns nets to 3D global routing grids/tracks to estimate congestion) and Detailed Routing (which places actual metal tracks and vias while adhering to foundry Design Rule Manual DRM rules).

Question 6

What is the difference between Design Rule Checking (DRC) and Layout Versus Schematic (LVS)?

Accepted Answer

DRC verifies that physical layout metal widths, spacing, enclosure, and via dimensions comply with foundry manufacturing rules to prevent open circuits or short circuits. LVS compares the extracted physical layout netlist against the original schematic/gate-level netlist to confirm structural and electrical equivalence.

Question 7

What happens during Logic Synthesis when converting Verilog RTL to a Gate-Level Netlist?

Accepted Answer

Logic Synthesis reads high-level Verilog/VHDL RTL, parses language constructs into generic boolean logic (GTECH), applies timing constraints (SDC), and maps the design onto target technology standard cells from target technology libraries. It optimizes for area, power, and delay while generating a gate-level netlist and SDC constraints for PnR.

Question 8

Why is TCL scripting essential for physical design engineers working with Innovus and ICC2?

Accepted Answer

Tool Command Language (TCL) is the standard scripting language across electronic design automation (EDA) tools like Synopsys ICC2, Cadence Innovus, PrimeTime, and Design Compiler. Physical design engineers use TCL to automate design imports, customize placement and routing commands, extract custom timing reports, query netlist attributes via dbGet or get_attribute, and execute unattended batch flows.

Question 9

What is Scan Insertion and why is it performed during front-end/physical design?

Accepted Answer

Scan Insertion converts standard sequential flip-flops into scan flip-flops connected into serial shift chains. This allows Automatic Test Pattern Generation (ATPG) tools to shift test vectors into internal registers during post-silicon manufacturing test, detecting stuck-at faults and transition faults before chip packaging.

Question 10

What is the Short-Channel Effect (SCE) in sub-micron MOSFETs and how does it impact physical design?

Accepted Answer

As MOSFET channel length shrinks in sub-nanometer nodes, the drain voltage exerts greater control over the channel, causing threshold voltage roll-off, Drain-Induced Barrier Lowering (DIBL), subthreshold leakage power increase, and mobility degradation. Physical design mitigates SCE through multi-VT cell selection, FinFET/GAA architecture library adoption, and careful power domain management.

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